The present invention generally relates to the surface treatment of semiconductor materials, and in particular to treating substrates for fabricating components for microelectronic and/or optoelectronic applications. More precisely, the invention concerns a method of reducing the roughness of the free surface of a semiconductor wafer that includes an annealing step to smooth the free surface.
The term “free surface” means the surface of a wafer which is exposed to the external environment (in contrast to an interface surface which is in contact with the surface of another wafer or some other element).
As explained below, the invention can be implemented in a particularly advantageous, but non-limiting manner, in combination with a method of fabricating thin films or layers of semiconductor material of the type described in U.S. Pat. No. 5,374,564. A method that uses the teaching of the above-cited document is known as the SMART-CUT® method. In outline, its main steps are as follows: implanting atoms beneath a face of a semiconductor substrate (in particular silicon), in an implantation zone of the substrate, bonding the implanted substrate onto a stiffener substrate by intimate contact, and detaching the implanted substrate in its implantation zone, or zone of weakness, to transfer the portion of the substrate that is situated between the surface that was subjected to implantation and the implantation zone to the stiffener, to form a thin film or semiconductor layer thereon.
The term “implanting” atoms means any bombardment of atomic or ionic species suitable for introducing the species into the material of the wafer, with the implanted species having a concentration maximum at a predetermined depth within the wafer relative to the bombarded surface, so as to define a zone of weakness. The depth of the zone of weakness is a function of the nature of the implanted species, and the implantation energy associated therewith. In this text, the generic term “wafer” may be used to designate the film or layer transferred by such a SMART-CUT® type method. The wafer (which is made of semiconductor material) can thus be associated with a stiffener, and possibly also with other intermediate layers.
The term “wafer” is also used in the present text to mean any wafer, layer, or film of semiconductor material such as silicon, regardless of whether or not the wafer has been produced by a SMART-CUT® type method, the object being in all cases to reduce the roughness of the free surface of the wafer. For applications of the type mentioned above, the roughness specifications associated with the free surfaces of wafers are very severe and critical, and the quality of the wafer free surface is a parameter which determines the quality of components to be made on the wafer. It is thus common to find roughness specifications that must not exceed 5 angstroms (Å) in root mean square (rms) value.
Roughness measurements are generally performed using an atomic force microscope (AFM). Roughness is measured on surfaces that are scanned by the tip of the AFM microscope, covering areas in the range 1 micrometer (μm)×1 μm to 10 μm×10 μm, and sometimes 50 μm×50 μm, or even 100 μm×100 μm.
Roughness may be characterized in two ways. First, the roughness can be described as a “high frequency” roughness and corresponds to scanning areas of about 1 μm×1 μm. Second, the roughness is a “low frequency” roughness when scanning corresponds to scanning areas of about 10 μm×10 μm or greater. The 5 Å specification example given above is thus for roughness corresponding to a scan area of 10 μm×10 μm.
Wafers produced by known methods (such as the SMART-CUT® type or other layer detachment methods) present surface roughnesses of values that are greater than the specifications of the magnitude specified above, unless the surface of the wafer is subjected to a specific treatment, such as polishing. A first known method for reducing the surface roughness of wafers consists of subjecting the wafer to “conventional” heat treatment (e.g. sacrificial oxidation). However, such treatment does not decrease the roughness of wafers down to the level of the above-mentioned specifications. In order to further reduce roughness, it is possible to envisage increasing the number of applications of conventional heat treatments, and/or combining them with other known methods. But such techniques lead to a method that is lengthy and complex. For example, U.S. Pat. No. 6,573,159 discloses a lengthy annealing process (about 60 minutes (mins)) at high temperature, followed by cooling under an atmosphere containing hydrogen.
A second known method consists of subjecting the free surface of the wafer to chemical-mechanical polishing. This method can indeed reduce the roughness of the free surface of the wafer. However, if a defect concentration gradient that increases towards the free surface of the wafer exists, this second method can also abrade the wafer down to a zone that presents an acceptable concentration of defects. But this second known method can compromise the uniformity of the free surface of the wafer. This drawback is worsened when a large amount of polishing is performed on the surface of the wafer, as would be necessary to reach the roughness levels mentioned above.
A third known method consists of subjecting the wafer to rapid annealing under a controlled atmosphere, known as rapid thermal annealing (RTA). In this text, this form of annealing is referred to either by its acronym RTA or in full as “rapid thermal annealing”.
In this third method, the wafer is annealed at high temperature, which may lie in the range of about 1100° C. to 1300° C., for a period of 1 second to 60 seconds. In a first variant of this third type of method, an example of which is to be found in U.S. Pat. No. 6,171,965, the free surface of is smoothed by performing RTA of the wafer under an atmosphere consisting of a mixture generally comprising hydrogen in combination with reagent gases (HCl, HF, HBr, SF6, CF4, NF3, CCl2F2, etc.). In this first variant of the third method, the aggressive nature of the mixture constituting the annealing atmosphere enables the free surface of the wafer to be “etched”, thereby reducing its roughness. Although this first variant can present certain advantages, the aggressive nature of the mixture of gases of the atmosphere limits the use of such a method, and elements other than the free surface of the wafer may be exposed to the action thereof (the face of the wafer or the structure to which it is bonded that faces away from the free surface of the wafer may also be detrimentally affected, and sometimes also the annealing chamber may be detrimentally affected.). It can thus be necessary to take additional measures to protect those elements, which tends to make the method even more complex. The aggressive nature of the mixture that is used can, under some circumstances, also worsen defects in the wafer, resulting in the wafer requiring additional treatments. Furthermore, use of an annealing atmosphere made up of different gases, some of which are reactive, requires providing an installation for implementing such a method that can be relatively complex (feeds for different gases, safety measures and the like).
An implementation taught in U.S. Pat. No. 6,573,159 corresponds to the first variant of the third type of method. In that implementation, RTA is performed in an atmosphere that always contains hydrogen. In a second variant of the third type of method, the wafer is subjected to RTA under an atmosphere that does not attack the material of the wafer. Smoothing results not from etching the free surface of the wafer, but from rebuilding the surface of the wafer. In that case, the annealing atmosphere is typically made up of hydrogen mixed with argon or nitrogen. PCT application WO01/15215 in the name of SOITEC Silicon-On-Insulator Technologies, S.A. discloses an example of the second variant of the third type of method.
PCT application WO01/28000 discloses a finishing treatment that always comprises two annealing operations, including one RTA operation. The annealing operations are performed in an atmosphere containing hydrogen or argon. The two disclosed annealing operations both smooth the free surface of the wafer. The reduction in low frequency roughness is illustrated by the last column of Table 2 in that document, which shows in particular the effect of the second annealing operation following the RTA operation. With RTA treatment alone (“comparative example 1”), low frequency roughness after treatment is in nanometers (nm) rms. By implementing the two annealing operations as described in that document, the low frequency roughness is significantly improved, reaching values of 0.28 nm rms and 0.30 nm rms. The teaching of PCT application WO01/28000 is thus focused on performing two successive operations of smoothing by annealing (where smoothing is characterized by a reduction in low frequency roughness), with the first of those two annealing operations being RTA. However, the method taught by PCT application WO01/28000 is relatively lengthy and expensive to implement since it always requires two annealing operations for smoothing.
The present invention seeks to provide an improvement to the methods mentioned above by simplifying such methods further. In addition, it would also be advantageous to reduce any slip lines that can appear in the crystallographic structure of the material of the wafer, in particular as a result of heat treatment (such as that which might be applied to the wafer in order to detach it when performing a SMART-CUT® type method). It is known that such slip lines can result from heating different regions of the wafer in a non-uniform manner (this is particularly troublesome in furnaces presenting cold spots). Furthermore, hydrogen used in the prior art implementations is a gas that is relatively expensive, and there is a continuous effort to reduce the costs associated with wafer treatment methods. Finally, it would be particularly advantageous to be able to implement a method satisfying the above-mentioned objects in combination with the use of a SMART-CUT® type method.